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Freescale Semiconductor Advance Information
Document Number: LP1072 Rev. 0.3, 12/2005
LP1072
802.11a/b/g Baseband System Solution
1
1.1
Introduction
The LP1070 Family
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Functional Description . . . . . . . . . . . . . . . . . 4 4 LP1072 Interfaces . . . . . . . . . . . . . . . . . . . . . 10 5 Timers/Reset . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Pinout and Footprint . . . . . . . . . . . . . . . . . . 17 7 DC Electrical Specifications . . . . . . . . . . . . 24 8 Timing Characteristics . . . . . . . . . . . . . . . . . 26 9 Mechanical Dimensions . . . . . . . . . . . . . . . . 29 10 Development Support . . . . . . . . . . . . . . . . . 29 11 Appendix: Comparison of LP1071 and LP1072 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 12 Revision History . . . . . . . . . . . . . . . . . . . . . 31
Freescale Semiconductor's 802.11 LP1070 family consists of high-performance, highly optimized PHY and MAC baseband Wireless LAN processors that fully implement the IEEE 802.11a, 802.11b and 802.11g PHY standards. These baseband processors are poised to revolutionize the Wireless LAN industry by setting new standards for power consumption, size, cost and performance. The LP1070 family is based on Freescale's proprietary Wireless Broadband Signal ProcessorTM (WBSPTM), an innovative and revolutionary receiver architecture that significantly reduces size and power consumption while providing maximum flexibility to support multiple wireless standards with no additional overhead. In addition to their superior performance and ultra low power consumption, the LP1070 processors provide the customers with the flexibility to tailor the chip characteristics to their needs. With software control, the
This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2005. All rights reserved. PRELIMINARY
Introduction
terminal manufacturers can tune the chip performance to get the exact balance they opt for when it comes to power consumption and performance.
1.2
General Description
The high-performance LP1072 baseband processor integrates the IEEE 802.11a/b/g PHY and full MAC functionality with the industry's lowest power consumption compared to any baseband processor in the market. The LP1072 was designed to target embedded devices and small form factor WLAN devices. Its support for SDIO and CompactFlash+ host interfaces combined with its ultra low power consumption and small size make it the optimal solution for mobile devices. It has been designed with a generic RF interface that lets it interface with virtually any RF components in the market. It has been fully tested to interface with RF solutions from Maxim and Airoha, thus providing terminal manufacturers with added flexibility in selecting the most appropriate RF parts based on their application and form factor. The LP1072's integrated ADC and DAC reduce the terminal manufacturers' bill of material and overall system cost. The integrated internal memory eliminates the need for external MAC memory, further reducing cost and saving valuable board space for small form factor devices. The LP1072 also provides the highest level of WLAN security by fully supporting WPA and AES.
1.3
* * * * * * * * * * * * * * * * * *
Features
Full compliance with 802.11a/b/g Ultra low power consumption, maximizing battery life and minimizing heat dissipation Ultra small package: 13.0 x 13.0 x 1.0 (max) mm Fully embedded ARM7TDMITM microprocessor for no load on the host processor, leading to maximum flexibility in supporting different host platforms Implementations of 802.11e Draft, for support of Quality of Service (QoS) real-time applications Support for WPA and AES, for enhanced security Automatic power management to reduce power consumption On-chip ADC and DAC to reduce system BOM and save on board area On-Chip PLL for clock generation On-chip ROM/RAM eliminating the need for external MAC memory Direct memory access (DMA) to reduce CPU utilization High throughput achieved using DMA Support of SDIO host interface Support of CompactFlash host interface Support of 16-bit SRAM emulation mode Serial EEPROM interface for initialization and device booting Eight General Purpose I/O (GPIO) pins for added flexibility UART interface to support diagnostic tools and general data transfer
LP1072 Advance Information, Rev. 0.3 2 PRELIMINARY Freescale Semiconductor
Specifications
* * * * *
JTAG Interface for testing and debugging Hardware engines for WEP, TKIP and AES support for less processor load Supports Direct Conversion (Zero-IF) radio architecture, saving RF components thus reducing BOM cost and simplifying board layout Generic RF interface that lets it work with virtually an WLAN RF components. Currently fully tested with RF from Maxim and Airoha. Total PHY flexibility in meeting customer requirements by providing software-controlled trade-off between competing performance metrics
2
Specifications
Table 1. Specifications
Feature Network Standard Support Network Architectures Data Rates Modulation Techniques Security Receiver Sensitivity (Using Maxim RF) IEEE 802.11 a/b/g Infrastructure, AdHoc 802.11 a/g: 6, 9, 12, 18, 24, 36, 48, 54 Mbps 802.11b:1, 2, 5.5, 11 Mbps BPSK, QPSK, 16QAM, 64QAM, CCK, OFDM, DSSS 40- and 128-bit WEP, TKIP, WPA, AES 802.11g 802.11b 6 Mbps:-91.0 dBm1Mbps:-97.1 dBm 9 Mbps: -89.7 dBm2 Mbps: -93.6 dBm 12 Mbps: -87.3 dBm5.5Mbps: -92.2 dBm 18 Mbps: -85.8 dBm11Mbps: -89.5 dBm 24 Mbps:-81.4 dBm 36 Mbps: -78.3 dBm 48 Mbps: -74.8 dBm 54Mbps: -73.0 dBm Receive:150 mW avg (@54Mbps) Listen: 132 mW Sleep:Less than1 mW I/O: 3.3 0.3 Vdc Core:1.8 5% Vdc 0 oC to +70 oC; < 95% humidity SDIO; compliant with SDIO Card Specifications, Version 1.00 CompactFlash+; compliant with CF+ and Compact Flash Specs Rev 2.0 16-bit SRAM emulation mode JTAG 8 GPIO pins One UART Serial EEPROM Microsoft Windows CE.net 3.0, 4.2 Microsoft Pocket PC 2002, 2003 Details
Power Consumption
Supply Voltage Operating Temperature Host Interfaces
Other Interfaces
Operating System Support
LP1072 Advance Information, Rev. 0.3 Freescale Semiconductor PRELIMINARY 3
Functional Description
Table 1. Specifications (continued)
Feature Packaging Options Semiconductor Technology RF Support Certification Details 200-pin VFBGA, 13.0 x 13.0 x 1.0(max) mm 0.18 micron Maxim, Airoha Wi-Fi(R) (incl. WPA), WQHL, FCC Part 15
3
Functional Description
LP1072 Chip Boundary
On-Chip RAM/ROM
Figure 1 is a functional block diagram of the LP1072.
Shared Memory
ARM7TDMI
MAC Subsystem
Memory Controller Protocol Accelerator Subsystem ARM Interface WEP Engine Generic Host Interface Shared Memory Controller AHB AES Engine 802.11 Protocol Accelerator
AHB
ARM Subsystem
PHY Subsystem
AFE
AFE Control I/Q ADC I/Q DAC Aux ADC
AHB Bridge Watchdog Timer Interrupt Controller SDIO Registers Clock Control Clock Gating
ARM Interface MAC-PHY Interface WBSPTM
UART JTAG EEPROM Interface GPIO RMB Registers
APB+
Aux DAC Host Interface
Clock Select Logic
DMA
RSSI ADC
PLL
CLKIN
(From TCXO)
Figure 1. Functional Block Diagram
3.1
Embedded Processor Subsystem
The embedded Processor Subsystem consists of the following: * An embedded ARM7TDMI microprocessor running at 88 MHz * An ARMTM Peripheral Subsystem accessed via an extended APB (APB+) bus
LP1072 Advance Information, Rev. 0.3 4 PRELIMINARY Freescale Semiconductor
Functional Description
3.1.1
UART
The UART is used for testing and diagnostic purposes and is capable of supporting data transfer rates of up to 115.2 kbps.
3.1.2
TBA
JTAG
3.1.3
Serial EEPROM Interface
The LP1072 supports an external serial EEPROM for storing the boot loader, MAC address, calibration data and any other vendor-specific data. The LP1072 supports serial EEPROMs of sizes from 8 Kbit (organized as 1024 entries of 8 bits each, or 1024 x 8) up to 512 Kbit (organized as 65,536 x 8). Serial EEPROMs from the following vendors have been tested and verified to work with the LP1072: * ATMEL (http:/www.atmel.com) * ST Microelectronics (http://www.st.com) * Microchip Technology (http://www.microchip.com) * Catalyst Semiconductor (http://www.catsemi.com) * Integrated Silicon Solutions, Inc. (http://www.issi.com) The EEPROM is supported through GPIOs. There is no dedicated hardware to support either I2C or SPI serial EEPROMs. The operating frequency of the serial EEPROM port is 400 kHz with a supply voltage of 3.0 V.
3.1.4
GPIO
To support vendor-specific needs, the LP1072 provides eight bi-directional General Purpose Input Output (GPIO) pins. Each pin can be independently configured as an input, output or an interrupt source. On reset, the GPIOs default as inputs, i.e. output drivers enables will be inactive.
3.1.5
RMB Registers
This block contains all the reset logic for both CPUs contained in the BRC and chip-wide reset control. It also defines controls for memory address re-mapping.
3.1.6
TBA
Watchdog
3.1.7
TBA
Interrupt Controller
LP1072 Advance Information, Rev. 0.3 Freescale Semiconductor PRELIMINARY 5
Functional Description
3.1.8
TBA
SDIO Registers
3.1.9
TBA
Clock Control
3.1.10
Clock Gating
This block contains all the control logic required to gate individual sub-block clocks.
3.2
3.2.1
Media Access Control (MAC) Subsystem
Protocol Accelerator Subsystem (PAS)
The main function of the Protocol Accelerator Subsystem is to provide hardware acceleration functions for the MAC Software to perform the time critical aspects of the 802.11 protocol. The PAS contains the following: * Shared Memory Controller - provided arbitrated access to the shared memory (MAC memory) * WEP Hardware Engine * AES Hardware Engine * 802.11 Protocol Accelerator - for support of time-critical MAC functions * Generic Host Interface
3.2.2
AES Block
The contents of the AES block are: * AES encryption/decryption core that performs AES encryption/decryption of a 128bit block. * Offset Codebook (OCB) mode encipher/decipher wrapper that performs OCB mode key generation for the AES core. * DMA controller and Shared Memory Interface that controls the reading/writing of data blocks from/to the PAS shared memory controller. * Control Registers, used to configure the operation of the AES block.
3.2.3
TBA
WEP Block
3.3
TBA
PHY Subsystem
LP1072 Advance Information, Rev. 0.3 6 PRELIMINARY Freescale Semiconductor
Functional Description
3.4
Analog Front End (AFE)
The Analog Front End (AFE) block consists of three Analog-to-Digital Converters (ADCs) and two Digital-to-Analog Converters (DACs) as given in Table 2.
Table 2. AFE Components
Component I/Q ADC I/Q DAC RSSI ADC Auxiliary ADC Auxiliary DAC Description A 2-channel ADC whose digital output serves as input to digital baseband and whose input is the differential signal from the RF (RX mode). A 2-channel DAC whose digital input is from baseband and output is a differential signal for the RF (TX mode). A single ended, single channel ADC A single ended, single channel ADC A single ended, single channel DAC Resolution 8-bit 8-bit 6-bit 8-bit 8-bit Clock 22 Msps 44 Msps 10 Msps 1 Msps 20 Msps
3.4.1
I/Q ADC
Table 3. I/Q ADC Specifications
Parameter Condition -- -- -- Fixed capacitance Switched capacitance @Fs Min -- 22 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -1 Typ 8 -- 11 1 1 4 1.0 0.5 -48.5 -47 48.5 47 7.2 7.0 0.2 0.5 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +1 Units bit MHz MHz pF pF cycles LSB LSB dB dB dB dB bit bit dB Degree LSB
I/Q ADC specifications are shown in Table 3.
Resolution Maximum Sampling Frequency Signal Bandwidth Input impedance
Latency Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Total Harmonic Distortion (THD) Fin= 1MHz Fin= 10MHz SNR Fin= 1MHz Fin= 10MHz ENOB Fin= 1MHz Fin= 10MHz Channel-to-Channel mismatch Gain Phase DC offset after calibration
-- -- --
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Functional Description
Table 3. I/Q ADC Specifications (continued)
Parameter Wake-up time Condition From Shutdown From Standby Min -- -- Typ -- -- Max 1 10 Units ms s
3.4.2
I/Q DAC
Table 4. I/Q DAC
Parameter Condition -- -- -- -- -- -- Min -- 44 -- 0.7 10 -- -- -- -- -- -- -- -- -- -- -- -- From Shutdown From Standby -1 -- -- Typ 8 -- 11 Vcmo1 -- -- 1.0 0.5 -48.5 -47 48.5 47 7.2 7.0 0.2 0.5 -- -- -- Max -- -- -- 1.5 -- 5 -- -- -- -- -- -- -- -- -- -- +1 10 2 Units bit MHz MHz V Kohm pF LSB LSB dB dB dB dB bit bit dB Degree LSB s s
I/Q DAC specifications are shown in Table 4.
Resolution Maximum Update rate 3dB Signal Bandwidth Output common-mode voltage Load
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Total Harmonic Distortion (THD) Fin= 1MHz Fin= 10MHz SNR Fin= 1MHz Fin= 10MHz ENOB Fin= 1MHz Fin= 10MHz Channel-to-Channel mismatch Gain Phase DC offset after calibration Wake-up time
-- --
1
See Analog input pin for definition of I/Q DAC output common-mode level.
LP1072 Advance Information, Rev. 0.3 8 PRELIMINARY Freescale Semiconductor
Functional Description
3.4.3
RSSI ADC
Table 5. RSSI ADC Specifications
Parameter Condition -- -- -- -- -- -- Fin= 100 kHz Min -- 10 0 -- -- -- -- Typ 6 -- -- 3 1.0 0.5 5.5 Max -- 6 6 -- -- -- -- Units bit MHz V cycles LSB LSB bit
RSSI ADC specifications are shown in Table 5.
Resolution Maximum Sampling Frequency Input Voltage Range Latency Integral Nonlinearity (INL) Differential Nonlinearity (DNL) ENOB
3.4.4
Aux ADC
Table 6. Aux ADC Specifications
Parameter Condition -- -- -- -- -- -- Fin= 100 kHz Gain Phase Min -- 1 0 -- -- -- -- -- -- -- -- Typ 8 -- -- 9 1.0 0.5 7.2 0.2 0.5 -- -- Max -- -- AVdd -- -- -- -- -- -- 10 2 Units bit MHz V cycles LSB LSB bit dB Degree s s
Aux ADC specifications are shown in Table 6.
Resolution Maximum Sampling Rate Input Voltage Range Latency Integral Nonlinearity (INL) Differential Nonlinearity (DNL) ENOB Channel-to-Channel mismatch
Wake-up time
From Shutdown From Standby
LP1072 Advance Information, Rev. 0.3 Freescale Semiconductor PRELIMINARY 9
LP1072 Interfaces
3.4.5
Aux DAC
Table 7. Aux DAC Specifications
Parameter Condition -- --
1
AUX DAC specifications are shown in Table 7.
Min -- 20 0.1 5 -- -- -- -- -- -- -- --
Typ 8 -- -- -- -- 5 80 1.0 0.5 7.2 -- --
Max -- -- 2.4 -- 10 -- -- -- -- -- 10 2
Units bit MHz V kOhm pF ns ns LSB LSB bit s s
Resolution Maximum Update rate Output voltage for full scale input Load
-- -- --
Propagation delay (tpd) Settling time (ts) Integral Nonlinearity (INL) Differential Nonlinearity (DNL) ENOB Wake-up time Fin = 1 MHz
-- -- -- --
From Shutdown From Standby
1
Due to saturation of the output buffer, INL and DNL are not applicable for output voltages below 200 mV. Output is monotonic above 0.1 V.
4
4.1
LP1072 Interfaces
SDIO Host Interface
The LP1072 supports SDIO Card Specifications, Version 1.00 (http//www.sdcard.org). The LP1072 SDIO host interface supports the I/O mode of the SD Card Specifications.
4.1.1
SDIO Supported Features
The features supported by the LP1072 SDIO host interface are: * SD 1-Bit Mode * SD 4-Bit Mode * Low Speed * Full Speed (25 MHz) * Interrupt * CMD52 during Data Transfer * CMD53 Multi Block Transfer * Interrupt during 4-bit Multiple Block Data Transfer
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LP1072 Interfaces
*
Combo Card (I/O mode only)
4.1.2
SDIO Function 0/1
For Function 0 registers descriptions, refer to SDIO Card Specification. For Function 1, the SDIO registers occupy a 128 Kbyte space as defined in the SDIO specification. Figure 2 illustrates SDIO Function 1 128 Kbyte Memory Map and Table 8 details its registers.
Bit7 0x0000 Reserved Bit0 0x0015 Reserved
0x0016 Reserved 0x0017 ARM to Host Interrupt Enable register 0 0x0018 ARM to Host Interrupt Enable register 1 0x001C SDIO Mailbox semaphore 0 0x001D SDIO Mailbox semaphore 1 0x001E SDIO Mailbox semaphore 2 0x0020 0x000E Watchdog Reset Register 0x000F SDIO Host to Device Interrupt Register 0 0x0010 0x0011 0x0012 0x0013 0x0014 Reserved Reserved Reserved ARM to Host Interrupt Source register 0 ARM to Host Interrupt Source register 1 0x27FF 0x2800 0x3FFF 0x4000 8Kbyte Internal Memory 0x5FFF
Figure 2. SDIO Function 1 128 Kbyte Memory Map
Reserved 2 KByte Mailbox space RAM0 RAM1 RAM2 Reserved 0x200E 0x200F 0x23FF 0x2400
0x1FFF 0x2000
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LP1072 Interfaces
Table 8. SDIO Function 1 Registers
Bit Name Description ARM Access HOST Access Reset
Watchdog Status Register (offset 0x000E) 0 Wdog_reset This is a read only bit that when `1' indicates that the LP1072 ASIC has had a watchdog reset occur. -- R R 0
7:1
Reserved
--
--
--
SDIO Host to Device Interrupt request register 0 (0x000F) 7:0 Write_sdio_arm_int Each bit in this register is 1 of 8 ARM interrupt requests from the SDIO Host to the device ARM. The Host should request an interrupt by writing a "1" to the corresponding bit in this register. The register will be read as a "1" until the ARM clears the register. Once the ARM has cleared the register then the corresponding bit will be read as "0" again. -- RW 0's
Device to SDIO Host Interrupt Source register 0 (0x0013) 7:0 Arm_to_sdio_int_clr[7:0] for writes. Arm_to_sdio_int_src[7:0] for reads. This register contains the interrupt pending status of the SDIO Host interrupt from the device. The device is capable of generating up to 8 individual requests. Each bit in this register is ANDed with the corresponding ARM to SDIO Host Interrupt enable register. The ANDed bits are then ORed together to generate a single SDIO Host interrupt in the cccr register space. To clear a particular interrupt bit the SDIO Host should write a "1" to that particular bit in this register. -- RW 0's
Device to SDIO Host Interrupt Source register 1 (0x0014) 2:0 Arm_to_sdio_int_clr[10:8] for writes. Arm_to_sdio_int_src[10:8] for reads. This register contains the interrupt pending status of the SDIO Host semaphore 0-2 host granted indication. When the Host requests a semaphore the corresponding interrupt will be triggered when the host has been granted the interrupt. Bit 0 is semaphore 0; bit 1 is semaphore 1; and bit 2 is semaphore 2. Each bit in this register is ANDed with the corresponding ARM to SDIO Host Interrupt enable register. The ANDed bits are then ORed together to generate a single SDIO Host interrupt in the cccr register space. To clear a particular interrupt bit the SDIO Host should write a "1" to that particular bit in this register. -- - RW 0's
7:3
Reserved
-
-
-
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LP1072 Interfaces
Table 8. SDIO Function 1 Registers (continued)
Bit Name Description ARM Access HOST Access Reset
Device to SDIO Host Interrupt Enable 0 (0x0017) 7:0 Arm_to_sdio_inte_en[7:0] Individual bit enables for each of the device to host interrupt source bits. Setting the corresponding bit to a "1" enables the interrupt; "0" disables the interrupt. The SDIO Host can disable all interrupts by disabling the main SDIO host interrupt in the CCCR register. - RW 0's
Device to SDIO Host Interrupt Enable 1 (0x0018) 2:0 Arm_to_sdio_inte_en[10:8] Individual bit enables for each of the device to host interrupt source bits. Setting the corresponding bit to a "1" enables the interrupt; "0" disables the interrupt. The SDIO Host can disable all interrupts by disabling the main SDIO host interrupt in the CCCR register. Bit 0 is enable for semaphore 0 granted; bit 1 is semaphore 1; and bit 2 is semaphore 2. Reserved - RW 0's
7:3
-
-
-
-
SDIO Host Mailbox Semaphore 0 Register (offset 0x001C) 1:0 Sdio_mbxp_0_sema 2 bit semaphore register to control whether the host or the device has access to the shared mailbox ram 0. The host should write a "01" to this register to request the shared ram 0. After writing "01" the host should read this register. If the value is "01" then the host owns access to the mailbox. If the value read is "11" then the device owns access to the mailbox. When the host is done utilizing the mailbox then it should release ownership of the mailbox by writing "00" to this register. - RW RW 0's
7:2
Reserved
-
-
-
SDIO Host Mailbox Semaphore 1 Register (offset 0x001D) 1:0 Sdio_mbxp_1_sema 2 bit semaphore register to control whether the host or the device has access to the shared mailbox ram 1. The host should write a "01" to this register to request the shared ram 1. After writing "01" the host should read this register. If the value is "01" then the host owns access to the mailbox. If the value read is "11" then the device owns access to the mailbox. When the host is done utilizing the mailbox then it should release ownership of the mailbox by writing "00" to this register. - RW RW 0's
7:2
Reserved
-
-
-
LP1072 Advance Information, Rev. 0.3 Freescale Semiconductor PRELIMINARY 13
LP1072 Interfaces
Table 8. SDIO Function 1 Registers (continued)
Bit Name Description ARM Access HOST Access Reset
SDIO Host Mailbox Semaphore 2 Register (offset 0x001E) 1:0 Sdio_mbxp_2_sema 2 bit semaphore register to control whether the host or the device has access to the shared mailbox ram 2. The host should write a "01" to this register to request the shared ram 2. After writing "01" the host should read this register. If the value is "01" then the host owns access to the mailbox. If the value read is "11" then the device owns access to the mailbox. When the host is done utilizing the mailbox then it should release ownership of the mailbox by writing "00" to this register. - RW RW 0's
7:2
Reserved
-
-
-
992 byte Mailbox RAM 1 (offset 0x200F to 0x23FF) 7:0 Mbox_rdata_1[15:0] Shared SDIO Mailbox. Both the ARM and Host can use the mailbox for message exchange between the SDIO device and the SDIO Host. Prior to accessing the SDIO Mailbox the Host should request and be granted the mailbox via the mailbox semaphore 1 register described above. Once the Host has been granted access to the mailbox it may read/write the mailbox however it likes. If the Host has not been granted access to the mailbox it will not be able to read or write the mailbox. Once the Host is finished with the mailbox it should release control of the mailbox as described in the mailbox semaphore 1 register. RW RW -
1 Kbyte Mailbox RAM 2 (offset 0x2400 to 0x27FF) 7:0 Mbox_rdata_2[15:0] Shared SDIO Mailbox. Both the ARM and Host can use the mailbox for message exchange between the SDIO device and the SDIO Host. Prior to accessing the SDIO Mailbox the Host should request and be granted the mailbox via the mailbox semaphore 2 register described above. Once the Host has been granted access to the mailbox it may read/write the mailbox however it likes. If the Host has not been granted access to the mailbox it will not be able to read or write the mailbox. Once the Host is finished with the mailbox it should release control of the mailbox as described in the mailbox semaphore 2 register. RW RW -
LP1072 Advance Information, Rev. 0.3 14 PRELIMINARY Freescale Semiconductor
LP1072 Interfaces
Table 8. SDIO Function 1 Registers (continued)
Bit Name Description ARM Access HOST Access Reset
8 Kbyte Internal Memory Buffer RAM (offset 0x4000 to 0x5FFF) 7:0 Imem_rdat[15:0] This is an internal memory buffer for specific use by the SDIO device. Data is read or written to this memory via SDIO cmd 53 reads or writes. Then, the SDIO DMA controller is used to move the data from the internal memory buffer to/from shared memory under device (ARM) control. - RW -
4.2
CompactFlash+ Host Interface
The LP1072 supports CF+ and Compact Flash Specification Revision 2.0. The LP1072 CF host interface supports both the I/O and storage modes of the Compact Flash Specifications. The interface allows an external host (or an host DMA) to have 8-bit or 16-bit memory and I/O mode access to the device according to the Compact Flash Specification 2.0.
4.3
SRAM Emulation Mode
The SRAM emulation mode provides an alternative write/read access to the device without using the CF port (or SDIO) using generic SRAM access cycles. It supports 16-bit memory interface. This mode is host-dependent and can be enabled and tested for a specific host.
4.4
4.4.1
* 1. 2. 3. * * * * * * *
RF Interface
Serial Programmable Interface (SPI)
The SPI is composed of 3 signals: RF_SIF_0_SCLK (serial clock) RF_SIF_1_CS_N (chip select) RF_SIF_2_DIN (data input) The serial information is sent to the RF transceiver in 18 bit bursts framed by chip select. The 18 bits comprises of leading 14 (or less) data bits and trailing 4 address bits Programming clock edges are ignored until chip select goes active low. All bits are shifted in on the rising edge of the clock and latched in when chip select returns inactive high. (permissible for the clock in either state) The interface can be programmed in any operating mode. Serial information is clocked in with the most significant bit (MSB) first. The address bits for the internal registers are decoded on the rising edge of chip select. The rising edge of chip select initiates an internal parallel load pulse that latches the last 18-bit serially shifted-in data into the internal register.
LP1072 Advance Information, Rev. 0.3 Freescale Semiconductor PRELIMINARY 15
Timers/Reset
5
Timers/Reset
The TCXO generates the 40MHz RFIC 800 mV clipped sine wave reference clock. The TCXO output is converted to a digital signal via a clock squarer input pad circuit. The 40 MHz TCXO reference is used to generate the 40 MHz IQDAC clock and the 20 MHz IQADC clock. The PLL synthesizes a reference from the 40 MHz reference. The reference is then used to generate the BRC, ARM, PAS and Symbol Processor clocks, the 44 MHz IQ DAC clock and the 22 MHz IQ ADC clock. When the TCXO and PLL are powered down the only active clock source is the 32 kHz XTAL, a.k.a. the Slow Clock. The TCXO, PLL and XTAL clock references all include bypass MUXes which allow the individual clock reference to be driven by an external signal. Figure 3 illustrates the high level clocking of the LP1072 with the associated pins.
Chip Boundary
PLL_BYPAS S PLL_BYPASS_CLK
40 MHz
88 MHz TCXO_BYPASS TCXO_BYPASS_CLK
ARM
TCXO
40 MHz
PLL
Clock Control Cuircuits
44 MHz 20 MHz 22 MHz
AFE
FAST_CLK_PWR XTAL_BYPASS XTAL_BYPASS_CLK
32 kHz
XTAL
32 kHz
Figure 3. LP1072 Clocks
5.1
System Clock
The LP1072 is clocked using an external crystal oscillator (XO) or a temperature compensated crystal oscillator (TCXO) running at 40MHz with a frequency resolution of 20 ppm or better.
5.2
PLL Block
PLL Bypass
5.3
Low Frequency Clock
The LP1072 uses a low power 32 kHz crystal oscillator to maintain the timing during sleep.
LP1072 Advance Information, Rev. 0.3 16 PRELIMINARY Freescale Semiconductor
Pinout and Footprint
6
6.1
S
Pinout and Footprint
Pinout
Table 9. Pin Description
Pad Name Pad Type Direction Description Pin
Power and Ground Pads VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE Clocks and Resets and Mode ARM_DBGEN EMBEDDED_RESET_N PLL_BYPASS PLL_BYPASS_CLK pdidgz pdisdgz pdidgz pdidgz Input Input Input Input ARM7TDMI Icebreaker debug enable pin Embedded board reset Bypass the internal PLL and use PLL_BYPASS_CLK PLL bypass clock input F3 F15 D10 A11 pvdd2dgz pvdd2dgz pvdd2dgz pvdd2dgz pvdd2dgz pvdd2dgz pvss2dgz pvss2dgz pvss2dgz pvss2dgz pvss2dgz pvss2dgz pvss2dgz pvss2dgz pvdd1dgz pvdd1dgz pvdd1dgz pvdd1dgz pvdd1dgz pvss1dgz pvss1dgz pvss1dgz pvss1dgz pvss1dgz pvss1dgz N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 3.3V I/O power pad (22 mA per pad max current) 3.3V I/O power pad (22 mA per pad max current) 3.3V I/O power pad (22 mA per pad max current) 3.3V I/O power pad (22 mA per pad max current) 3.3V I/O power pad (22 mA per pad max current) 3.3V I/O power pad (22 mA per pad max current) I/O ground pad (94mA max current) I/O ground pad (94mA max current) I/O ground pad (94mA max current) I/O ground pad (94mA max current) I/O ground pad (94mA max current) I/O ground pad (94mA max current) I/O ground pad (94mA max current) I/O ground pad (94mA max current) 1.8V core power pad (31 mA per pad max current) 1.8V core power pad (31 mA per pad max current) 1.8V core power pad (31 mA per pad max current) 1.8V core power pad (31 mA per pad max current) 1.8V core power pad (31 mA per pad max current) Core ground pad (25mA per pad max current) Core ground pad (25mA per pad max current) Core ground pad (25mA per pad max current) Core ground pad (25mA per pad max current) Core ground pad (25mA per pad max current) Core ground pad (25mA per pad max current) K3 P3 M6 N11 R14 E12 K5 L5 L6 L8 M11 K11 G11 F11 G1 R8 M10 K15 B15 H5 L7 L9 J11 E11 E9
LP1072 Advance Information, Rev. 0.3 Freescale Semiconductor PRELIMINARY 17
Pinout and Footprint
Table 9. Pin Description (continued)
Pad Name AVDD_PLL AVSS_PLL TAVDDPOWER DVDD_PLL DVSS_PLL TXCO_BYPASS TXCO_BYPASS_CLK XTAL_BYPASS XTAL_BYPASS_CLK FAST_CLK_POWER XTAL_32K_XIN XTAL_32K_XOUT RESET_N CHIP_MODE0 CHIP_MODE1 CHIP_MODE2 CHIP_MODE3 JTAG JTAG_RESET JTAG_CLOCK JTAG_DI JTAG_DO JTAG_MODE ARM Sub-system Signals ARM_GPIO0 ARM_GPIO1 ARM_GPIO2 ARM_GPIO3 ARM_GPIO4 ARM_GPIO5 ARM_GPIO6 ARM_GPIO7 ARM_UART_0_DI ARM_UART_0_DO ARM_EEPROM_DAT_GPIO pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Input Output Bi-dir General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O UART input data UART output data General Purpose I/O dedicated for EEPROM R1 N3 R3 N4 P4 N5 P5 R5 N7 P6 M7 pdudgz pdisdgz pdudgz pdo02cdg pdudgz Input Input Input Output Input Tap reset Tap clock Tap data in Tap data out Tap Mode P8 M8 R10 N10 R11 pdisdgz pdidgz pdidgz pdidgz pdidgz Pad Type pdiana2p pdiana2p pvdd3p pdiana2p pdiana2p pdidgz pdidgz pdidgz pdidgz pdo02cdg pdxoe4dg Direction N/A N/A N/A N/A N/A Input Input Input Input Output Analog Analog Input Input Input Input Input Analog 1.8 volt Analog ground 3.3 volt power for ESD Diodes 1.8 volt digital power for PLL 1.8 volt digital ground for PLL Bypass the TCXO and use the TCXO_BYPASS_CLK TCXO bypass clock Bypass XTAL osc and use XTAL_BYPASS_CLK XTAL bypass clock Enable the TCXO 32kHz crystal (NOTE: Must be placed next to PVDD1DGZ.) 32kHz crystal Chip Reset Chip Mode Select 0000 = SDIO normal operation 0001 = CF+ normal operation All other modes are reserved Description Pin C1 D1 E3 E1 E2 C11 D11 D15 D13 C10 C15 C14 E13 G2 J1 H3 K1
LP1072 Advance Information, Rev. 0.3 18 PRELIMINARY Freescale Semiconductor
Pinout and Footprint
Table 9. Pin Description (continued)
Pad Name ARM_EEPROM_CLK_GPIO Pad Type pdb04dgz Direction Bi-dir Description General Purpose I/O dedicated for EEPROM Pin N8
SDIO Signals (other signals on interface are 1 Vdd and 2 Vss pins) CD/DAT3 (connector pin 1) DAT[2] (connector pin 9) DAT[1] (connector pin 8) DAT[0] (connector pin 7) CMD (connector pin 2) CLK (connector pin 5) CF + (PC Card I/O Mode) CF_D0 CF_D1 CF_D2 CF_D3 CF_D4 CF_D5 CF_D6 CF_D7 CF_D8 CF_D9 CF_D10 CF_D11 CF_D12 CF_D13 CF_D14 CF_D15 CF_CE1_N CF_CE2_N CF_A0 CF_A1 CF_A2 CF_A3 CF_A4 CF_A5 CF_A6 CF_A7 pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdusdgz pdusdgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Input Input Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir CompactFlash data CompactFlash data CompactFlash data CompactFlash data CompactFlash data CompactFlash data CompactFlash data CompactFlash data CompactFlash data CompactFlash data CompactFlash data CompactFlash data CompactFlash data CompactFlash data CompactFlash data CompactFlash data CF Card enable even address (8 bit mode) Chip Enable odd address (8 bit mode) CompactFlash address CompactFlash address CompactFlash address CompactFlash address CompactFlash address CompactFlash address CompactFlash address CompactFlash address F2 G4 G3 H1 J2 H2 J3 L1 K4 L2 L3 M2 L4 M3 P1 P2 R2 M4 R4 M5 N6 R6 R7 P7 R9 N9 pduw04dgz pdu04dgz pdu04dgz pdu04dgz pdu04dgz pdisdgz Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Input Card detect/data 3 Data 2 Data 1/interrupt Data 0/busy indication Command/response Clock H4 K2 J4 M1 N1 N2
LP1072 Advance Information, Rev. 0.3 Freescale Semiconductor PRELIMINARY 19
Pinout and Footprint
Table 9. Pin Description (continued)
Pad Name CF_A8 CF_A9 CF_A10 CF_OE_N CF_IORD_N CF_IOWR_N CF_WE_N CF_IREQ_N CF_RESET CF_CD1_N CF_CD2_N CF_INPACK_N CF_STSCHG_N CF_REG_N AFE Interface AGND AGNDIQADC AGNDIQDAC AVDD AVDDIQADC AVDDIQDAC VDDIQADC VSSIQADC VDDIQDAC DGND DVDD IBIAS VBG VREFN VREFP AUXADCIN_0 AUXADCIN_1 AUXADCIN_2 pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pvdd3p pvss3p pvdd3p pvss1dgz pvdd1dgz pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Input Input Input Input Input Analog ground Double bonded with Analog Reference negative supply) Analog ground Analog ground Analog 3.3 volt Analog 3.3 volt Analog 3.3 volt 3.3 volt power for ESD Diodes 3.3 volt ground for ESD Diodes 3.3 volt power for ESD Diodes Digital Ground Digital 1.8 Volt Pin for monitoring or bypassing bias current, flowing out of the pin to agnd. Voltage reference pin for decoupling (equal to 1.25V). Connect 1uF(ceramic) + 100nF (ceramic) to agndref. ADC Negative reference for decoupling ADC Positive reference for decoupling Muxed analog input to auxiliary ADC bit 0 Muxed analog input to auxiliary ADC bit 1 Muxed analog input to auxiliary ADC bit 2 E6 E8 D8 A3 D7 A9 A4 E7 D2 B2 C2 B3 B5 A5 A7 C5 D5 B4 Pad Type pdb04dgz pdb04dgz pdb04dgz pdusdgz pdusdgz pdusdgz pdusdgz pdt04dgz pdudgz pdt04dgz pdt04dgz pdt04dgz pdo04dgz pdusdgz Direction Bi-dir Bi-dir Bi-dir Input Input Input Input Output Input Output Output Output Output Input CompactFlash address CompactFlash address CompactFlash address CF common or attribute memory indication I/O read in conjunction with reg and ce1/2 I/O write in conjunction with reg and ce1/2 Common or attribute memory write enable I/O mode interrupt request (pulsed low or level sensitive) Reset Card detect Card detect Decode indication (not widely implemented) Status Change Cycle indication Description Pin P9 P10 R13 N12 P12 P13 R15 N14 P15 L13 K12 J12 K14 J14
LP1072 Advance Information, Rev. 0.3 20 PRELIMINARY Freescale Semiconductor
Pinout and Footprint
Table 9. Pin Description (continued)
Pad Name IADCINN IADCINP QADCINN QADCINP RSSIADCIN VOCM AUXDACOUT IDACOUTP IDACOUTN QDACOUTP QDACOUTN EXT_BIAS TCXO Squarer AVDD_TCXO AVSS_TCXO CLKIN RF Interface Signals RF_ANALOG_LDO RF_EN RF_RXEN RF_TXEN RF_PAEN1 RF_PAEN2 RF_SPARE1 RF_SPARE2 RF_VGA6 RF_VGA5 RF_VGA4 RF_VGA3 RF_VGA2 RF_VGA1 RF_VGA0 RF_RXHP RF_ANTENNA_SEL RF_ANTENNA_SEL_N pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdo02cdg pdo02cdg pdo02cdg pdo02cdg pdo02cdg pdo02cdg pdo02cdg Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Bi-dir Output Output Output Output Output Output Output LDO enable for RF VCO power. Driven by PHY controller. RF enable. Driven by PHY controller. RF Rx enable. Driven by PHY controller. RF Tx enable. Driven by PHY controller. RF PA enable 1. Driven by PHY controller. RF PA enable 2. Driven by PHY controller. RF spare 1 (not used). Driven by PHY controller. RF spare 2 (not used). Driven by PHY controller. RF VGA setting. Driven by UWA. RF VGA setting. Driven by UWA. RF VGA setting. Driven by UWA. RF VGA setting. Driven by UWA. RF VGA setting. Driven by UWA. RF VGA setting. Driven by UWA. RF VGA setting. Driven by UWA. RF Rx highpass filter setting. Driven by UWA. RF antenna select. Driven by ARM. RF antenna select. Driven by ARM. M9 R12 P11 N13 P14 M13 L12 G13 M14 N15 M15 K13 L14 L15 J13 H12 H13 J15 pvdd3p pvss3p pdiana2p N/A N/A Input Analog 3.3 volt Analog ground TCXO reference clock input F4 G5 F1 Pad Type pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p Direction Input Input Input Input Input Input Output Output Output Output Output Input Negative input of I-ADC Positive input of I-ADC Negative input of Q-ADC Positive input of Q-ADC RSSI ADC input Input pin for definition of IQDAC output common -mode level Auxiliary DAC output Positive output of I-DAC Negative output of I-DAC Positive output of Q-DAC Negative output of Q-DAC External Bias for test Description Pin A8 B8 B6 C6 B1 D9 C4 B9 C9 B10 A10 D4
LP1072 Advance Information, Rev. 0.3 Freescale Semiconductor PRELIMINARY 21
Pinout and Footprint
Table 9. Pin Description (continued)
Pad Name RF_SIF_2_DIN RF_SIF_1_CS_N RF_SIF_0_SCLK RF_LOCK_DETECT Pad Type pdo02cdg pdo02cdg pdo02cdg pdidgz Direction Output Output Output Input Description RF 3-wire serial interface. Driven by ARM. RF 3-wire serial interface. Driven by ARM. RF 3-wire serial interface. Driven by ARM. RF lock detect. Read by ARM. Pin G12 H14 G15 G14
6.2
pdisdgz pdidgz pdudgz pdusdgz pdddgz
Pad Descriptions
32 kHz crystal pad (1 pad w/2 pad connections) Schmitt triggered input 5 Volt tolerant 5 Volt tolerant input pad 5 Volt tolerant input pad w/internal pullup Schmitt Trigger Input Pad, 5V-Tolerant w/pullup Input Pad With Pulldown, 5-VT IO CMOS 2 mA output CMOS 4 mA output CMOS 3 state output pad w/input (5 volt tolerant) CMOS 3 state output pad w/input (5 volt tolerant) CMOS 3-State Output Pad with Schmitt Trigger Input and Pullup, 5V-Tolerant CMOS 3-State Output Pad with Input and Pulldown, 5V-Tolerant CMOS 3-State Output Pad with Input and Pulldown, 5V-Tolerant CMOS 3-State Output Pad with Input and Pulldown, 5V-Tolerant CMOS 3-State Output Pad, 5V-Tolerant CMOS 3-State Output Pad with Input and Pullup, 5V-Tolerant 3-State Output Pad with Input and Enable Controlled Pull-Up, 5V-Tolerant Low Frequency Analog I/O for use with power cut diodes (Note: It is recommended to utilize the secondary ESD protection circuit: ESND on these pads.
pdxoe4dg
pdo02cdg pdo04cdg pdb04dgz pdb02dgz pdu02sdgz pdd04dgz pdd04dgz pdd08dgz pdt04dgz pdu02dgz pduw02dgz pdiana2p
LP1072 Advance Information, Rev. 0.3 22 PRELIMINARY Freescale Semiconductor
Pinout and Footprint
6.3
1 A NC 2 NC
Footprint
3 AVDD 4 5 6 NC 7 VREFP 8 9 10 11 12 13 NC 14 NC 15 NC PVDD3P VREFN _2 AUXADC IN_2 VBG IADCINN AVDDIQDAC QDACOUTN PLL_ RE_1 BYPASS SERVED _CLK IADCINP IDACOUTP QDACOUTP NC IDACOUTN RESERVED NC NC
B RSSIADC IN C AVDD_ PLL AVSS_ PLL DVDD_ PLL CLKIN VDD_ CORE _1
DGND DVDD
IBIAS NC
QADCINN
NC NC
NC NC
NC XTAL_ 32K_ XOUT
VDD_CORE _5 XTAL_32K_ XIN XTAL_ BYPASS RESERVED
AUXDAC AUXADC QADCINP OUT IN_0 EXT_ BIAS AUXADC IN_1 AGND TAVSSP OWER AVSS_ TCXO GND NC
FAST_CLK TCXO_ _POWER BYPASS PLL_ BYPASS GND
D
PVDD3P _1
NC
AVDDIQADC AGNDIQ DAC_1 PVSS3P_2 AGNDIQ ADC
VOCM
TCXO_ REBYPASS SERVED _CLK GND GND GND
XTAL_ REBYPASS SERVED _CLK
E F G
DVSS_ TAVDD PVSS3P PLL POWER _1 CF_D_0 CHIP_ MODE _0 CF_D_5 ARM_ AVDD_ DBGEN TCXO CF_D_2 CF_D_1
AGND
GND
VDD_IO_ RESET_N RE6 SERVED
REREREEMBEDDED SERVED SERVED SERVED _RESET_N RF_SIF_ 2_DIN RF_ RXHP RF_ SPARE2 RF_ RF_SIF_0_ LOCK_ SCLK DETECT RESERVED
H CF_D_3
CHIP_ SD_DAT MODE_ _3 2
GND
RF_ RF_SIF_ ANTENNA 1_CS_N _SEL
J
CHIP_ MODE _1 CHIP_ MODE _3 CF_D_7
CF_D_4 CF_D_6 SD_DAT _1 SD_DAT_ VDD_IO CF_D_8 2 _1 CF_D_9 CF_D_ CF_D_12 10
GND
GND
CF_ RF_VGA_ CF_REG RF_ INPACK_ 0 _N ANTENNA N _SEL_N CF_CD2_ RF_VGA_ CF_ N 3 STSCHG _N VDD_ CORE_4
K
GND
GND
L
GND
GND
GND
GND JTAG_ CLOCK ARM_ EEPROM _CLK_ GPIO JTAG_ RESET VDD_ CORE_2
GND RF_ ANALOG _LDO CF_A_7
GND VDD_CORE _3 JTAG_DO
GND GND
RF_ CF_CD1_ RF_VGA RF_VGA_1 SPARE1 N _2 NC RF_PAEN RF_VGA RF_VGA_4 2 _6 RF_ TXEN CF_IREQ RF_VGA_5 _N
M SD_DAT_ CF_D_11 CF_D_ CF_CE2 CF_A_1 VDD_IO_3 ARM_ 0 13 _N EEPROM_ DAT_GPIO N SD_CMD SD_CLK ARM_ ARM_ GPIO_1 GPIO_3 ARM_ GPIO_5 CF_A_2 ARM_ UART _0_DI CF_A_5
VDD_IO_ CF_OE_ 4 N
P CF_D_14 CF_D_15 VDD_IO ARM_ _2 GPIO_4 R ARM_ CF_CE1_ ARM_ CF_A_0 GPIO_0 N GPIO_2
ARM_ GPIO _6 ARM_ GPIO_7
ARM_ UART _0_DO CF_A_3
CF_A_8
CF_A_9
RF_RXE CF_ N IORD_N JTAG_ MODE RF_EN
CF_ IOWR_N
RF_ PAEN1
CF_ RESET
CF_A_4
CF_A_6
JTAG_DI
CF_A_10 VDD_IO_ CF_WE_N 5
LP1072 Advance Information, Rev. 0.3 Freescale Semiconductor PRELIMINARY 23
DC Electrical Specifications
7
7.1
DC Electrical Specifications
Absolute Maximum Ratings
Table 10. Absolute Maximum Ratings
Parameter Supply Voltage (3.0 V) Supply Voltage (1.8 V) Input Voltage DC Output Current Storage Temperature Electrostatic Discharge Voltage Min -0.3 -0.3 GND - 0.3 TBD TBD TBD Max 4.0 2.2 VDD + 0.3 TBD TBD TBD Units V V V mA
o
C
V
Operating the LP1072 under conditions that exceed Absolute Maximum Ratings may result in permanent damage to the device. Absolute maximum ratings are limiting values, and are considered individually, while all other parameters are within their specified operating ranges.
7.2
Recommended Operating Conditions
Table 11. Recommended Operating Conditions
Parameter Supply I/O Voltage Supply Core Voltage Operating Temperature Symbol VDD_IO VDD_C TA Min 3.0 1.71 0 Max 3.6 1.89 70 Units V V
oC
Recommended operating conditions are shown in Table 11.
Thermal dissipation (for multi-layer PCB) is shown in Table 12.
Table 12. Thermal Dissipation (for multi-layer PCB)
# PCB Layers # PCB Vias PCB Trace Density JEDEC JEDEC 6% JA (C/W) 0 m/s 96.1 81.7 66.9 1 m/s 68.9 60.2 51.3 2 m/s 59.6 52.6 45.8 JT (C/W) 1.0 0.9 0.7 JC (C/W) 6.5 6.2 6.0
1 (1s) 2 (2s)
0 36 0
LP1072 Advance Information, Rev. 0.3 24 PRELIMINARY Freescale Semiconductor
DC Electrical Specifications
7.3
DC Characteristics
Table 13. DC Characteristics
Parameter Symbol VDD VD33 VIL VIH VT VT+ VTII IOZ Schmitt Schmitt VI =VD33 or 0V VOH = VSS VOL = VDD Condition -- -- -- -- -- Min 1.62 3.0 -0.3 2.0 1.46 1.47 0.90 -10 -10 -10 -- 2.4 2.2 4.5 TBA 1 TBA 2 TBA TBA 12.3 18.5 22.7 36.9 Typ 1.8 3.3 -- -- 1.58 1.50 0.94 -- -- -- -- -- 3.3 6.6 TBA 19.7 TBA 39.5 TBA TBA 24.8 37.1 49.5 74.3 Max 1.98 3.6 0.8 5.5 1.75 1.50 0.96 10 10 10 0.4 -- 3.8 7.6 TBA 22.7 TBA 45.4 TBA TBA 38 56.9 75.9 113.9 Units V V V V V V V A A A V V mA mA mA mA mA mA mA mA mA mA mA mA
DC characteristics are shown in Table 13.
Pre-driver Supply Voltage I/O Supply Voltage Low-level input voltage High-level input voltage Threshold point Schmitt Trigger Low to High Thresh Schmitt Trigger High to Low Thresh Input Leakage Current 3-state leak current
Output low voltage Output high voltage Low Level Out Current @VOL=0.4V
VOL VOH IOL
IOL = 2,4,..., 24mA IOH =2,4,..., 24mA 2 mA 4 mA 8 mA 12 mA 16 mA 24 mA
High Level Out Current @VOH=2.4V
IOH
2 mA 4 mA 8 mA 12 mA 16 mA 24 mA
LP1072 Advance Information, Rev. 0.3 Freescale Semiconductor PRELIMINARY 25
Timing Characteristics
8
8.1
8.1.1
Timing Characteristics
AFE Interface
I/Q ADC
Figure 4. Timing of the Pipelining Operation in I/Q ADC
8.1.2
I/Q DAC
Figure 5. Timing Diagram of the I/Q DAC Inputs and Outputs
LP1072 Advance Information, Rev. 0.3 26 PRELIMINARY Freescale Semiconductor
Timing Characteristics
8.1.3
RSSI ADC
Figure 6. Timing of the RSSI ADC Pipelining Operation
Figure 7. Timing of the Aux ADC Successive Approximation Operation
LP1072 Advance Information, Rev. 0.3 Freescale Semiconductor PRELIMINARY 27
Timing Characteristics
8.1.4
Auxiliary DAC
Figure 8. Conversion Cycle in Normal Operation for Aux DAC Table 14. Aux DAC Timing Parameters
Symbol tpd ts Parameter Propagation delay Settling time Min -- -- Typ 5 80 Max -- -- Units ns ns
LP1072 Advance Information, Rev. 0.3 28 PRELIMINARY Freescale Semiconductor
Mechanical Dimensions
9
Mechanical Dimensions
The LP1072 is a 200-pin Very-thin Fine-pitch Ball Grid Array (VFBGA) package. All dimensions are mm.
Figure 9. LP1072 Package
10 Development Support
In addition to the LP1072 baseband and MAC, Freescale provides developers with reference designs, development platform, software drivers, system development software, testing and debugging tools and a full set of technical documentation that includes: * User Guide * Data Sheet * Schematics * Gerber Files * Application Notes Freescale also provides multi-interface reference designs to aid device manufacturers with today's demanding time-to-market requirements.
LP1072 Advance Information, Rev. 0.3 Freescale Semiconductor PRELIMINARY 29
Appendix: Comparison of LP1071 and LP1072
11 Appendix: Comparison of LP1071 and LP1072
Table 15. Comparison of LP1071 and LP1072
Item Network Standard Support Network Architectures Data Rates Modulation Techniques Security Receiver Sensitivity1 LP1071 IEEE 802.11 a/b/g Infrastructure, AdHoc 802.11 a/g: 6, 9, 12, 18, 24, 36, 48, 54 Mbps 802.11b: 1, 2, 5.5, 11 Mbps BPSK, QPSK, 16QAM, 64QAM, CCK, OFDM, DSSS 40- and 128-bit WEP, TKIP, WPA, AES 802.11g802.11b 6 Mbps:-91.0 dBm1 Mbps:-97.1 dBm 9 Mbps: -89.7 dBm2 Mbps:-93.6 dBm 12 Mbps: -87.3 dBm5.5Mbps:-92.2 dBm 18 Mbps: -85.8 dBm11Mbps:-89.5 dBm 24 Mbps: -81.4 dBm 36 Mbps: -78.3 dBm 48 Mbps: -74.8 dBm 54Mbps: -73.0 dBm Receive:150 mW avg (@54Mbps) Listen:132 mW Sleep:Less than 1 mW I/O: 3.0 - 3.6 Vdc Core:1.8 5% Vdc 0 oC to +70 oC; < 95% humidity SDIO SDIO CompactFlash Plus (CF+) 16-bit SRAM emulation mode JTAG, 8 GPIOs, 1 UART, Serial / EEPROM Microsoft Windows CE.net 3.0 and 4.2 Microsoft Pocket PC 2002, 2003 144-pin VFBGA, 9 x 9 x 1.0 mm 200-pin VFBGA, 13 x 13 x 1.0 mm LP1072
Power Consumption
Supply Voltage Operating Temperature Host Interface
Other Interfaces Operating System Support Package Semiconductor Technology RF Support Reference Designs Certification
1
0.18 micron Airoha, Maxim SDIO CF+ Wi-Fi (incl. WPA), WHQL, FCC Part 15
Using Maxim RF
LP1072 Advance Information, Rev. 0.3 30 PRELIMINARY Freescale Semiconductor
Revision History
12 Revision History
This document's updated format reflects that Freescale Semiconductor, Inc. acquired CommASIC on October 20, 2005. Since the release of the previous version of this document (Rev. 0.2), the technical content has not been updated.
LP1072 Advance Information, Rev. 0.3 Freescale Semiconductor PRELIMINARY 31
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Document Number: LP1072 Rev. 0.3 12/2005
PRELIMINARY

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